View 33899_1523039.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

document number: mc33899 rev. 2.0, 6/2007 freescale semiconductor advance information * this document contains certain information on a new product. specifications and information herein are subject to change without notice. ? freescale semiconductor, in c., 2007. all rights reserved. programmable h-bridge power ic the 33899 is designed to drive a dc motor in both forward and reverse shaft rotation under pulse- width modulation (pwm) control of speed and torque. a current mirror output provides an analog feedback signal proportional to the load current. a serial peripheral interface (spi) is used to select slew rate control, current compensation limits and to read diagn ostic status (fau lts) of the h- bridge drive circuits. spi diagnostic reporting includes open circuit, short circuit to vignp, short circui t to ground, die temperature range, and undervoltage on vignp. features ? drives inductive loads in a full h-bridge configuration ? current mirror output signal (gain selectable via external resistor) ? short circuit current limiting ? thermal shutdown (outputs latched off until reset via spi) ? internal charge pump circuit for the internal high-side mosfets ? spi-selectable slew rate control and current limit control ? overtemperature shutdown ? outputs can be disabled to high-impedance state ? pwm-able up to 11 khz @ 3.0 a ? synchronous rectification cont rol of the high-side mosfets ? low r ds(on) outputs at high junction temperature (< 165 m ? @ ta = 125 c, vignp = 6.0 v) ? outputs survive shorts to -1.0 v ? pb-free packaging designated by suffix code vw figure 1. 33899 simplified application diagram programmable h- bridge power ic vw suffix (pb-free) 98ash70693a 30-pin hsop ordering information device temperature range (t a ) package mc33899vw/r2 -40c to 125c 30 hsop 33899 33899 redis cres vccl s1 s0 rs vignp vcc vddq csns fwd rev pwm en1 en2 cs sclk d1 d0 lscmp gnd v ignp +5.0 v v ddl mcu
analog integrated circuit device data 2 freescale semiconductor 33899 internal block diagram internal block diagram figure 2. 33899 simplifi ed internal block diagram gate drives current sense, limitation, and mirror charge pump to gate drives s1 s0 direction and pwm control fwd rev pwm en1 en2 vignp baseline slew rate set rs temperature sense and shutdown command, fault, and temperature register sclk di do vddq gnd +3.3 v regulator vcc vccl csns cres cs lscmp pwm override redis m3 m4 m2 m1 internal
analog integrated circuit device data freescale semiconductor 3 33899 pin connections pin connections figure 3. 33899 pin connections table 1. 33899 pin definitions a functional description of each pin can be found in the functional pin description section beginning on page 12 . pin number pin name formal name definition 1 vddq logic level output bias sets v oh level of do output and lscmp. 2 do spi data out spi control data output pin from the ic to the mcu. 3 di spi data in spi control data input pin from the mcu to the ic. 4 sclk spi serial clock input the sclk input is the clock signal input for synchronization of serial data transfer. 5 cs chip select (active low) this pin is an input connected to a chip select output of an mcu. 6 cres charge pump this pin connects an exter nal capacitor, which is the storage reservoir for the internal charge pump. 7 redis automatic output re- enable disable this input pin is a connecti on to a capacitor that determines the default time the output will be turned off when the low-side current comparator is tripped, if pwm has not commanded it. the typical value with a 0.1 f is 100 s. if shorted, the feature is disabled. 8, 9, 22, 23 vignp protected ignition voltage this input pin is the primary h-bridge power input. note: not reverse voltage protected. 10, 11 s0 bridge output 0 to load these output pins drive the bi-directi onal motor and must be connected together on the pc board. 12, 19 gnd ground these pins must be connected on the pc board to the exposed pad. 13, 17, 18 nc no connect these pins have no internal connections. 14 lscmp low-side comparator this output pin pulses high anytime the low-side current comparator is tripped. 15 16 en2 en1 master enable 2 master enable 1 these input pins determine the mode of the ic; namely, sleep, standby, and run. 20, 21 s1 bridge output 1 to load these output pins drive the bi-directi onal motor and must be connected together on the pc board. vddq 1 cs cres redis vignp vignp s0 s0 gnd nc lscmp en2 di sclk do csns fwd pwm rs vignp vignp s1 s1 gnd nc nc en1 vccl rev vcc 7 8 9 10 11 12 13 14 15 3 4 5 6 2 30 24 23 22 21 20 19 18 17 16 28 27 26 25 29 tab tab
analog integrated circuit device data 4 freescale semiconductor 33899 pin connections 24 rs slew rate control this input pin is connected to a resistor that sets slew timing. 25 pwm pwm input this input pin is used to set the motor switching and frequency duty cycle. 26 fwd forward input this input pin, along with the reverse input pin rev, determines the direction of current flow in the h-bridge. 27 rev reverse input this input pin, along with the forward i nput pin fwd, determines the direction of current flow in the h-bridge. 28 vccl 3.3 v input 3.3 v input source. 29 vcc 5.0 v input 5.0 v input source. 30 csns current sense output of current amplifier. tab/pad thermal interface / gnd exposed pad thermal interface the exposed pad, a thermal interface for si nking heat from the device, is a high- current gnd connection and must be c onnected to gnd (pins 12 and 19). table 1. 33899 pin de finitions (continued) a functional description of each pin can be found in the functional pin description section beginning on page 12 . pin number pin name formal name definition
analog integrated circuit device data freescale semiconductor 5 33899 electrical characteristics maximum ratings electrical characteristics maximum ratings table 2. maximum ratings all voltages are with respect to ground unless otherwise no ted. exceeding these ratings may cause a malfunction or permanent damage to the device. ratings symbol value unit electrical ratings protected power supply voltage v ignp - 0.3 to 40 v logic supply voltage v cc - 0.3 to 7.0 v logic output bias voltage v ddq - 0.3 to 7.0 v vccl supply voltage v ccl - 0.3 to 5.0 v input / output voltage (fwd, rev, en1, en2, pwm, cs , di, sclk, do, csns, lscmp, rs, redis) v i / o - 0.3 to 7.0 v motor outputs v s0 , v s1 - 0.5 to 40 v charge pump voltage v cres - 0.3 to 50 v esd voltage (1) human body model machine model v esd1 v esd2 2000 200 v thermal ratings operating temperature (2) ambient junction t a t j - 40 to 125 - 40 to 150 c storage temperature t stg - 65 to 150 c thermal resistance, junction to ambient (3) r ja 18 c/w thermal resistance, junction to case (exposed pad) r jc <0.5 c/w peak package reflow temperature during solder mounting (4) t solder 220 c notes 1. esd1 testing is performed in accordance with the human body model (c zap = 100 pf, r zap = 1500 ? ), esd2 testing is performed in accordance with the machine model (c zap = 200 pf, r zap = 0 ? ). 2. the junction temperature is the primar y limiting parameter. the module thermal des ign must provide a low enough thermal imped ance to keep the junction temperature within limits for al l anticipated power levels and ambient temperatures. 3. r ja is referenced to jedec standard 2s2p thermal evaluation board at 1w total device power dissipation in still air. deviations fr om this standard will produce corresponding c hanges in the actual thermal performance. 4. pin soldering temperature limit is for 10 seconds maximum dura tion. not designed for immersion so ldering. exceeding these lim its may cause malfunction or permanent damage to the device.
analog integrated circuit device data 6 freescale semiconductor 33899 electrical characteristics static electrical characteristics static electrical characteristics table 3. static electric al characteristics characteristics at - 40 c t j +150 c, 4.75 v v cc 5.25 v, 3.14 v v ccl 3.47 v, 2.97 v v ddq 5.25 v, 6.0 v v ignp 26.5 v unless otherwise noted. typical values reflect the approximate parameter means at t a = 25c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit power input v ignp operating voltage v ignp 6.0 ? 26.5 v v ignp operating current v ignp = 14.5 v, h-bridge disabled, en1 = en2 = 5.0 v i vignp ? ? 10 ma v ignp sleep current en1 = en2 = 0 v i vignp ? ? 145 a undervoltage shutdown threshold v ignp uv 3.4 ? 4.2 v overvoltage shutdown threshold v ignp ov 27 ? 32 v v cc operating voltage v cc 4.75 ? 5.25 v v cc operating current @ 5.0 v i vcc ? ? 5.0 ma v cc sleep current en1 = en2 = 0 v i vcc ? ? 25 a v ccl operating voltage v ccl 3.14 ? 3.47 v v ccl operating current @ 3.3 v i vccl ? ? 3.0 ma v ccl sleep current en1 = en2 = 0 v i vccl ? ? 2.0 a v ddq operating voltage v ddq 2.97 ? 5.25 v v ddq operating current i vddq ? ? 200 a v ddq sleep current en1 = en2 = 0 v i vddq ? ? 50 a power-on reset power-on reset threshold v cc rising v cc por 3.9 ? 4.7 v power-on reset threshold v ccl rising v ccl por 2.50 ? 2.95 v power-on reset hysteresis v por hys 0.2 ? 0.5 v charge pump c res voltage (mosfets 1 and 3 or 2 and 4 on) i cres = - 0.1 ma v ignp = 6.0 v 9.5v v ignp 26.5 v v cres 14 v ignp + 10 ? ? ? 45 v control inputs input low voltage en1, en2, pwm, cs , sclk, di, fwd, rev v il ? ? 0.8 v input high voltage en1, en2, pwm, cs , sclk, di, fwd, rev v ih 2.0 ? ? v
analog integrated circuit device data freescale semiconductor 7 33899 electrical characteristics static electrical characteristics control inputs (continued) input leakage current ? digital inputs sclk, di: v in = 0 v i in - 5.0 ? 5.0 a input bias current en1, en2, fwd, rev, pwm: v in = 5.0 v cs : v in = 0 v i dwn i up 27 - 70 ? ? 70 - 27 a data output data output low voltage i ol = 1.6 ma v do_ol ? ? 0.4 v data output high voltage i oh = - 800 a v do_oh v ddq - 0.5 ? ? v data out tri-state leakage i leak - 5.0 ? 5.0 a power output breakdown voltage s0, s1, v ignp : i = 100 a v bvds 40 ? ? v on-resistance (each output fet) i out = 3.5 a, v ignp = 6.0 v r ds(on) ? ? 165 m ? body diode forward voltage (all 4 output diodes) (6) enx = 0 v, i out = 3.0 a, t j = 150 c enx = 0 v, i out = 3.0 a, t j = 23 c enx = 0 v, i out = 3.0 a, t j = -40 c v f ? ? ? ? ? ? 1.0 1.4 1.8 v off-state output bias vcc = 5.0 v, en1 = en2 = 0 v, s0 shorted to s1 (through motor) v bias 0.2 v cc ? 0.6 v cc v off-state output leakage (between so and s1) v cc = 0 v, en1 = en2 = 0 v, r l = 600 ? , v ign = 16 v v cc = 5.0 v, en1 = en2 = 0 v, r l = 600 ? , v ign = 18 v i leak ? ? ? ? 100 100 a fault threshold (off state) (en1 = en2 = 0 v) measured at s1 measured at s0 v fault_thr1 v fault_thr2 0.65 v cc 0.15 v cc ? ? 0.85 v cc 0.35 v cc v current sense current sense zero fwd = 5.0 v, rev = 0 v; then fwd = 0 v, rev = 5.0 v, i s1/s0 = 0 a i csz ? ? 0.2 ma current sense ratio: k csns = i s1/s0 / i cs (fwd = 5.0 v, rev = 0 v; then fwd = 0 v, rev = 5.0 v) i s1/s0 = - 0.4 a i s1/s0 = - 1.6 a i s1/s0 = - 6.0 a (7) k csns k csns k csns 250 340 ? ? ? 400 500 435 ? table 3. static electrical characteristics (continued) characteristics at - 40 c t j +150 c, 4.75 v v cc 5.25 v, 3.14 v v ccl 3.47 v, 2.97 v v ddq 5.25 v, 6.0 v v ignp 26.5 v unless otherwise noted. typical values reflect the approximate parameter means at t a = 25c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data 8 freescale semiconductor 33899 electrical characteristics static electrical characteristics current sense (continued) current sense saturation voltage fwd = 5.0 v, rev = 0 v; then fwd = 0 v, rev = 5.0 v, r csns = 10 k ? v csns_sat v cc - 0.2 ? v cc + 0.2 v high-side current limit di bit 4 and bit 3 = 00 di bit 4 and bit 3 = 01 di bit 4 and bit 3 = 10 (5) di bit 4 and bit 3 = 11 (5) i hslim 5.8 7.2 8.0 10.0 ? ? ? ? 10.2 11.9 13.5 17.9 a low-side current limit di bit 4 and bit 3 = 00 di bit 4 and bit 3 = 01 di bit 4 and bit 3 = 10 di bit 4 and bit 3 = 11 i lslim 5.3 6.4 7.4 10.0 ? ? ? ? 8.6 10.0 11.0 15.0 a low-side current limit comparator di bit 4 and bit 3 = 00 di bit 4 and bit 3 = 01 di bit 4 and bit 3 = 10 di bit 4 and bit 3 = 11 i lscmp 3.2 4.2 5.0 7.5 ? ? ? ? 5.2 6.4 7.5 10.6 a current limit current comparator differential di bit 4 and bit 3 = 00 di bit 4 and bit 3 = 01 di bit 4 and bit 3 = 10 di bit 4 and bit 3 = 11 i curlim - i lscmp 1.0 1.0 1.0 1.0 3.0 3.0 3.0 3.0 ? ? ? ? a lscmp output voltage i ol = 100 a i oh = -100 a v lscmp_ol v lscmp_oh ? v ddq -0.5 ? ? 0.1 v ddq v redis current pullup current source pulldown current sink i redis_sc i redis_sk -160 1.0 ? -70 5.0 a ma redis threshold voltage where low-side mosfet turns on voltage where low-side mosfet turns off hysteresis v redis_thr 3.6 3.35 0.15 ? ? ? 4.4 4.15 0.35 v thermal thermal shutdown (6) , spi bits = 11 t lim 157.5 ? 172.5 c thermal hysteresis (6) t hys 3.0 ? 10 c temperature warning (6) , spi bits = 01 t warn 132.5 ? 147.5 c temperature warning hysteresis (6) t warn(hys) 3.0 ? 10 c notes 5. production test at 125 c is at v ignp 18 v. operation to 26.5v is guaranteed by design. 6. guaranteed by characterization in t he development phase. parameter not tested. 7. design information, not production tested. table 3. static electrical characteristics (continued) characteristics at - 40 c t j +150 c, 4.75 v v cc 5.25 v, 3.14 v v ccl 3.47 v, 2.97 v v ddq 5.25 v, 6.0 v v ignp 26.5 v unless otherwise noted. typical values reflect the approximate parameter means at t a = 25c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data freescale semiconductor 9 33899 electrical characteristics dynamic electrical characteristics dynamic electrical characteristics table 4. dynamic electri cal characteristics characteristics at - 40 c t a 125 c, 4.75 v v cc 5.25 v, 6.0 v v ignp 26.5 v unless otherwise noted. typical values reflect the approximate parameter means at t a = 25c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit pwm frequency (8) f pwm ? ? 11 khz pwm / output duty cycle accuracy frequency = 10 khz, rs = 10 k ? , slew time = 1x, duty cycle = 50% out acc -4.5 ? 4.5 % short circuit filter (s0 and s1) t scf 5.0 ? 11 s minimum pwm low pulse width (8) pwm min ? ? 0.2 s low-side comparator one shot pulse duration after a low-side comparator trip t lsc 5.0 ? 10 s low-side comparator blank time blanking time after a low-side comparator pulse t lscb 5.0 ? 10 s overtemperature shutdown filter (time before die temp bit is set), (8) t otf 5.0 ? 13.5 s enable lead time (8) t lead 140 ? ? ns enable lag time (8) t lag 50 ? ? ns delay until output shuts off short circuit detection or en1 falling or en2 falling until h-bridge disables t sodly ? ? 5.0 s dead timer (9) time between high-side mosfet an d low-side mosfet transition t dead 1.0 ? 3.0 s open load fault delay duration of fault condition until fault gets latched in t fdo 200 ? 400 s overvoltage shutdown filter time from vignp > v ov to mosfet output disable t ovs 100 ? 200 s sleep recovery time (8)(9)(10) t sleep ? 150 ? s slew time s0 and s1 (11) (output load = 5.0 mh and 1.6 ?, 30% to 70% , v ignp = 14.5 v) slew mode = 1x rs= 50 k ? rs = 10 k ?, short slew mode = 2x rs = 50 k ? rs = 10 k ?, short slew mode = 4x rs = 50 k ? rs = 10 k ?, short s0 / s1 rs 1.6 0.2 2.8 0.5 5.0 1.2 ? ? ? ? ? ? 3.2 0.8 6.3 1.5 12.8 3.0 s notes 8. design information. 9. guaranteed by characterization in t he development phase. parameter not tested. 10. sleep recovery time is the time from en going high until the outputs are ready to respond to input. this time is dependent o n the recovery time of v ccl and v ccl_por . the recommended value for the v ccl capacitor is designed to permit initia lization of internal logic prior to clearing of the por condition ( see + 3.3 v input (v ccl ) on page 12 ). 11. by design, if the rs input is left open, the slew time is the same as when short ed to gnd. however, this is a high-impedanc e input and will be susceptible to external noise s ources unless terminated appropriately. it is highly recommended to terminate this pin with either a ground or one of the program resistors .
analog integrated circuit device data 10 freescale semiconductor 33899 electrical characteristics dynamic electrical characteristics spi characteristics (12) transfer frequency (13) f op dc ? 6.25 mhz sclk period (13) t sclk 160 ? ? ns sclk high time (13) t sclk_hs 56 ? ? ns sclk low time (13) t sclk_ls 56 ? ? ns di input setup time (13) t di(su) 16 ? ? ns di input hold time (13) t di(hold) 20 ? ? ns do access time t do(acc) ? ? 116 ns do disable time (14) t do(dis) ? ? 100 ns do output valid time t do(valid) ? ? 116 ns do output hold time (13) no capacitor on do t do(hold) 0 20 ? ns rise time (14) t r ? ? 60 ns fall time (14) t f ? ? 30 ns cs negated time (13) t cs n 500 ? ? ns input pins input capacitance (8) di sclk c in ? ? ? ? 20 20 pf notes 12. all spi timing is performed with a 100 pf load on do unless otherwise noted. 13. design information. 14. guaranteed by characterization. table 4. dynamic elec trical characteristics characteristics at - 40 c t a 125 c, 4.75 v v cc 5.25 v, 6.0 v v ignp 26.5 v unless otherwise noted. typical values reflect the approximate parameter means at t a = 25c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data freescale semiconductor 11 33899 electrical characteristics timing diagrams timing diagrams figure 4. spi timing diagram figure 5. shut off and enable delay figure 6. slew time measurement t lead t sclk_hs t sclk t lag t cs n t sclk_ls t do(valid) t do(hold) t do(dis) t do(acc) t di(su) t di(hold) t r , t f lsb in data msb in msb out data lsb out don?t care di do sclk cs t sodly 0.8v t endly v enx 2.0v 5.0v v s0-s1 @100ma 70% 30% 70% 30% s0/s1 rs s0/s1 rs v s0-s1
analog integrated circuit device data 12 freescale semiconductor 33899 functional description introduction functional description introduction the 33899 is a programmable h-bridge, power integrated circuit (ic) designed to drive dc motors or bi-directional solenoid controlled actuators, such as throttle control or exhaust gas recirculation actuat ors. it is particularly well suited for the harsh environment found in automotive power train systems. the key characteristic of this versatile driver is configurability. the selectable slew rate permits the customer to choose the slew rate needed for performance and noise suppression. the serial peripheral interface (spi) allows the system microprocessor to clear the fault register, select a programmable current limit and select the slew rate. a unique fault restart feature allows the part to be configured to maintain limited functionality ev en in the presence of some faults. the 33899 is designed to drive a bi-directional dc motor using pulse-width modulation (pwm) for speed and torque control. a current mirror output provides an analog feedback signal proportional to the load current. spi diagnostic reporting includes open circuit, short-to-battery, short-to- ground, die temperature range and under voltage. functional pin description vignp input (vignp) vignp is the primary power input for the h-bridge. the input voltage is 0 v to 26.5 v (40 v during a load dump transient). this pin must be externally protected against application of a reverse voltage (t hrough an external inverted n-channel mosfet, diode, or switched relay). + 5.0 v input (vcc) +5.0 v power input is required to power the internal analog circuitry and the +3.3 v internal regulator. + 3.3 v input (vccl) a +3.3 v internal regulator powers the internal digital circuitry. the internal supply cannot be used as a power source by any other ic in the system. this output can be overdriven by an external supply. the internal supply requires a 0.47 f capacitor on this output to insure proper startup sequencing when coming out of sleep mode. logic bias input (vddq) vddq supplies the level shifted bias voltage for the logic level outputs designed to be read by the microprocessor. this pin will apply the logic supply voltage to do and lscmp making the outp ut logic levels comp liant to logic systems from 3v to over 5v. outputs (s1 and s0) the s1 and s0 outputs drive the bi-directional dc motor. each output has two internal n-channel mosfets connected a half-bridge configuration between vignp and ground. only one internal mosfet is on at any one time for each output. the fwd, rev, and pwm inputs control the state of the h-bridge. the turn on / off slew times are determined by the selected rs resistor value and the spi slew time register contents (refer to table 8 , page 22 ). output polarity control (fwd/rev inputs) the fwd and rev inputs determine the direction of current flow in the h-bridge by directing the pwm input to one of the low-side mosfets (refer to table 5 ). when a change in the current direction is commanded via the microprocessor, the pwm must switch from one low-side mosfet to the other without shoot-through current in the h- bridge. the gate voltage of the low-side mosfets must drop below and remain below the gate threshold voltage for the ?dead time? before either of the high-side mosfets is commanded on. at no time are the high-side and low-side mosfets simultaneously on at the same side of the h- bridge. the fwd and rev inputs have 50 a pull-downs to ground that disable all the outputs should an open circuit condition occur. table 5. fwd / rev truth table enable inputs (en1, en2) logic [0] in either of the enables (en1 or en2) disables all four of the output drivers (refer to table 6 ). while either en1 or en2 is at logic [1], the 33899 is still capable of detecting open circuit and short circuit faults on all of the outputs interfacing with the external l oad(s). the en1 and en2 inputs have 50 a pull-downs to ground t hat disable the outputs when open circuit conditions occur. table 6. enable truth table fwd rev current direction 00 off 01 reverse 10 forward 11 off en1 en2 status 0 0 disabled (sleep mode)
analog integrated circuit device data freescale semiconductor 13 33899 functional description functional pin description input control of h-bridge (pwm) the pwm input pin controls the sequencing of the pwm?ing high-side and low-side mosfets. a logic [1] commands the appropriate low-side mosfet (m2 or m4) on and the appropriate high-side mosfet (m1 or m3) off. a logic [0] commands the appropriate low-side mosfets (m2 or m4) off and the appropriate high-side mosfets (m1 or m3) on. the high- and low-side mosfets that are pwm?ed are determined by the commanded direction (fwd or rev). if a shorted condition exists, the particular output mosfet will be latched off after 5.0 s to 10 s. subsequent pwm edges will retry to turn on the same mosfet. only when a thermal fault is reached are a ll outputs latched off until the clear fault bit is set by the microprocessor. any pwm high-to- low-to-high pulse that is shorter than 500 ns keeps the low- side mosfet from starting to tu rn off. the rising edge of this short pulse re-enables the low-side mosfet if the pulse width is at least 200 s long (if a short circuit latch-off had occurred during the previous positive pwm pulse). the pwm input has a 50 a pull-down to ground that disables all the outputs should an open circuit condition occur. figure 7. 33899 operation in current reversal 0 1 disabled (standby mode) 1 0 disabled (standby mode) 1 1 enabled (run mode) en1 en2 status forward current reverse current current in load reverses polarity both high side fet?s on until next pwm rising edge load current low side fet body diode high side fet body diode s0 s1 pwm fwd rev
analog integrated circuit device data 14 freescale semiconductor 33899 functional description functional pin description load current feedback (csns) the load current sense circuit mirrors a sample of the load current back to the microcontr oller via the csns pin. it supplies a current that is 1/400 th of the load current (see equation 1). an analog multiplexer routes the enabled high- side current to the csns pin. an external resistor connected to the csns pin (r csns ) sets current to voltage gain. the circuit operates properly in the presence of high-frequency noise. an external capacitor may be necessary to provide filtering. note this output is clamped so that it will not exceed v cc . charge pump reservo ir capacitor (cres) the charge pump provides an output voltage over the full operating vignp range that is sufficient to drive the output mosfets and ensure that the output r ds(on) specifications are met. an external reservoir capacitor of 0.1 f is recommended. the charge pump operates at approximately 2.0 mhz to 4.0 mhz in order to prevent interference with am entertainment radio. high-side and low-side slew time control (rs) the turn-on and the turn-off slew times on s0 and s1 (both low- and high-side drive out puts) are adjustable from 5.0 s (50 k ? rs) to 1.0 s (10 k ? rs) to reduce high-frequency harmonic energy in the vehicle?s wiring harness. in addition, slew time control is programmab le to be either 1x, 2x, or 4x (via the spi) to lower power dissipation at elevated die temperatures. the characteristics of the turn-on and turn-off voltage are linear, with no disc ontinuities, during the output driver state transitions. if the rs pin detects an impedance of less than 5.0 k ? to ground or greater than 1.0 m ? to ground, it defaults to the fastest slew time of 1.0 s. low-side comparator one shot output (lscmp) the lscmp output pin pulses high for 5 s to 10 s any time the low-side comparator is tripped. then the output goes low during a 5 s to 10 s blanking time. if another low-side comparator trip event is detected during the blanking time, another 5 s to 10 s pulse high occurs immediately after the blanking interval. figure 8. ls current comparator one shot automatic output re-enable disable (redis) the redis input pin automatically re-enables the low-side mosfet once the redis input voltage exceeds 4.0 v. an external capacitor (c redis ) determines the time interval (see equation 2). once a low-side curr ent comparator is tripped, a 120 a current source linearly charges the capacitor until either the next rising edge of pwm or the 4.0 v trip level is achieved. this re-enables the low-side output mosfet and discharges the capacitor to 0 v. this feature is disabled by grounding this input. as per the above equation, a 2.2 nf capacitor will provide a nominal 75 s time interval. v csns = i out 400 r csns . eq. 1 ls current comparator i load pwm lscmp 5 - 10 s pulse out 5 - 10 s blank time 5 - 10 s pulse out the redis min duration = 25 s, so c redis must be > 1 nf > 40 s 5 - 10 s 5 - 10 s c redis i . dt = dv c 120 a . 4.0 v = eq. 2
analog integrated circuit device data freescale semiconductor 15 33899 functional description functional pin description figure 9. re-enable after a low side current comparator trip low-side current comparator vs. current limit levels there are two different current limit thresholds for the low- side mosfets: current comparator and current limit. current comparator is the normal commanded switching current. current limit is for fault protection. the inductance of the load results in just the current comparator tripping. once t he low-side current comparator has tripped and filter time ex pired, the low-side mosfet turns off and the high-side mosfet subsequently turns on for normal current re-circulation in the load. if an actual hard short to either vignp or ground on the s0/s1 outputs is encountered, th e current limit kicks in and prevents large current spikes from vignp (or to ground) to occur. the threshold level of the current comparator vs. the high- and low-side current limits is given in the static electrical characteristics table, page 8 . as backup protection, ther e is a linear overcurrent controller to limit current spike during timer operations. serial peripheral interface (spi) the 33899 has a serial peripheral interface consisting of chip select ( cs ), serial clock (sclk), serial data out (do), and serial data in (di). this device is configured as a spi slave and is daisy-chainable (single cs for multiple spi slaves). chip select ( cs ) the cs is a low = true input that selects this device for serial transfers. on the falling edge of cs , the do pin is released from tri-state mode, and all status information is latched in the spi shift register. while cs is asserted, register data is shifted into the di pin and shifted out of the do pin on each subsequent sclk. on the rising edge of cs , the do pin is placed in a high impedance state and the fault register reloaded (latched) with the current filtered status data. to allow sufficient time to re load the fault register, the cs pin must remain low fo r a minimum of t csn prior to going high again. by design, the cs input is immune to spurious pulses of 50 ns or shorter. (do may come out of tri-state, but no status bits are cleared and no control bits are changed.) the cs input has a 50 a current source to vcc, which pulls this pin to v cc if an open circuit condition occurs. this pin has ttl-level compatible input voltages, which allows proper operation with microproce ssors using a 3.0 v to 5.0 v supply. serial clock (sclk) the sclk input is the clock signal input for synchronization of serial data transfer. this pin has ttl-level compatible input voltages, which allow proper operation with microprocessors using a 3.3 v to 5.0 v supply. when cs is asserted, both the microprocessor and the 33899 latch input data on the rising edge of sclk. the spi master typically shifts data ou t on the falling edge of sclk, while the 33899 shifts data out on the falling edge of sclk to allow more time to drive the do pin to the proper level. serial data output (do) the do is the spi data out pin. when cs is asserted (low), the msb is the first bit of the word transmitted on do and the lsb is the last bit of the word transmitted on do. after all 8 bits of the fault r egister are transmitt ed, the do output sequentially transmits the digital data that was just received on the di pin. this allows the processor to distinguish a shorted di pin condition. the do output continues to transmit ls current comparator pwm redis 4 vdc i load reset to 0 vdc reset to 0 vdc t = 33.3 * c (nf) s t min = 25 s t = 33.3 * c (nf) s t min = 25 s
analog integrated circuit device data 16 freescale semiconductor 33899 functional description functional pin description the input data from the di input until cs eventually transitions from a logic [0] to a logic [1]. the do output pin is in a high impedance condition unless cs is low, at least one enable pin is high and vcc and vccl are within the normal operating range. when active, the output is ?rail to rail?, depending on the voltage at the vddq pin. serial data input (di) the di input takes data from the microprocessor while cs is asserted (low). the msb is the first bit of each word received on di and the lsb is the last bit of each word received on di. the 33899 serially wraps around the di input bits to the do output after t he do output transmits its fault flag bits. the first 8 bits before cs goes high are latched into the control register. any byte s transmitted before the last 8 bits are just wrapped around to the do output and are not used by the 33899 (see figure 10 ). this pin has ttl-level compatible input voltages, which allow proper operation with microprocessors using a 3.3 v to 5.0 v supply. figure 10. spi operation with extended cs logic out bias (vddq) the vddq input pin provides the bias voltage for the data out buffer and ls comparator. it must be connected to the same power supply that is used by the microprocessor?s spi i / o. cs* di/ sclk do fault/temp data (1 byte) 1st di byte di control register (1 byte) not used (1 byte) cs di/ sclk do not used (1 byte) di control register (1 byte) first di byte fault/temperature data (1 byte)
analog integrated circuit device data freescale semiconductor 17 33899 functional internal block description introduction functional internal block description figure 11. functional block diagram introduction h-bridge output drivers (s0 and s1) the 33899 power ic provides the means to efficiently drive a dc motor in both forward and reverse shaft rotation via a monolithic h-bridge comprising low r ds(on) n-channel mosfets and integrated control circuitry. the switching action of the h-bridge can be pulse-width modulated to obtain both torque and speed co ntrol, with pwm frequencies up to 11 khz supported with minimal switching losses. the outputs comprise four power mosfets configured as a standard h-bridge, controlled by the pwm input and the fwd and rev inputs. analog control and protection the 33899 has integrated voltage regulators which supply the logic and protection functions internally. this reduces the requirements for external supplies and insures the device is safely controlled at all times when battery voltage is applied. an integrated charge pump provides the required bias levels to insure the output mosfets turn fully on when commanded. each mosfet provides feedback to the protection circuitry by way of a current sensor. each sense signal is compared with programmable over-current levels and produces an immediate shutdown in case of a high current short circuit. the low-side current sense is also capable of producing a current limiting pwm to reduce overload conditions as determined by the programmable limits. the high-side current sense is avai lable to the mcu as an analog current proportional to the load current. each mosfet has over-temperature protection circuitry that disables the device. a thermal warning sets a flag in the spi register when the device is approaching a protection limit. mcu interface and output control the spi and control logic signals are compatible with both 5v and 3.3v logic systems. the spi provides programmabl e control of output slew rate and current limits. the status register makes detailed diagnostics available for protective and warning functions. the output drivers are controll ed by the input signals en1, en2, fwd, rev, and pwm. the low-side and high-side mosfets connected to s0 are controlled by the pwm input when fwd is a logic [1] and rev is a logic [0]. the low-side mosfet connected to s1 is idle in this state. the high-s ide mosfet connected to s1 is statically on in the forward direction. the low-side and high- side mosfets connected to s1 are controlled by the pwm input when fwd is a logic [0] and rev is a logic [1]. the low- side mosfet connected to s0 is idle in this state. the high- side mosfet connected to s0 is statically on in the reverse direction. to reduce power during the recirculation period, the upper recirculation mosfet is turned on synchronously with the off-time of the low-side mosfet. spi interface direction control command and fault registers mcu interface and output control current sense voltage regulation temperature sense charge pump h-bridge output drivers s0 - s1 analog contro l and protection pwm controller
analog integrated circuit device data 18 freescale semiconductor 33899 functional internal block description introduction the pwm input is connected to the system microprocessor and provides for control of the four mosfet outputs. the pwm duty cycle ran ge is 0% to 100%; however, open load detection circuits require a minimum off-time. the 33899 holds all outputs off if both fwd and rev are either logic [0]s or logic [1]s. figure 12 depicts inputs versus outputs in forward mode operation. figure 12. 33899 operation in forward mode load current pwm input m1 gate m2 gate m3 is ?on? m4 is ?off? s0 v ignp + v f r ds(on) * i load v ignp - r ds(on) * i load dead time
analog integrated circuit device data freescale semiconductor 19 33899 functional device operation operational modes functional device operation operational modes short-to-gnd or short-to-vignp fault filtering the 33899 has a short-to-gnd and short-to-vignp digital fault filter. after a single fault occurrence, another 7 shorts consecutive with pwm must be detected befor e the bit is latched into the fault register. short to -1.0 v on output devices the 33899 can survive a short to -1.0 v through a 300 m ? impedance (10 khz to 1000 khz) and a direct short to - 0.5 v on all i/os that exit the module. a shorted output to these voltages does not impact correct fault diagnostics for the effected channel or any other normal operation of the 33899. this feature applies to the so and s1 outputs as well. loss of module ground loss of ground condition at th e parts level denotes that all pins of the 33899 see very low impedance to ignition. in the application, a loss of ground condition results in all i/o pins floating to ignition voltage v ignp , while all externally referenced i/o pins are at worst case pulled to ground. loss of module ignition supply loss of ignition condition at the parts level denotes that the power input pins of the 33899 see infinite impedance to the ignition supply voltage (depending on the application) but there is some undefined impedance from these pins to ground. output driver load(s) the 33899 is capable of driving any pwm?ed inductive load of up to 3.5 a of continuous average current (at a maximum frequency of 11 khz) with current feedback capability. the 33899 drives etc (electronic throttle control) motors. the typical c haracteristics of the etc motor are as follows: ? resistance 1.25 ? to 2.4 ? (lumped resistance due to actuator, harness, and connectors) over the temperature range. ? inductance 800 h at 1000 hz over the temperature range. output power density the die area for the output mosfets provides an adequate thermal resistance to limit junction temperature to 150c when the device is o perated at 11 khz, 3.5 a continuous average current, and a 2.0 ms nominal transition time. this applies to fr4 pc board with a metal pedestal under the device, which provides a thermal path to the case of the module. output synchronous rectification control the 33899 uses synchronous rectification to reduce the power dissipation during the recirculation period. in order to prevent shoot-through current, the 33899 has a dead time circuit that turns on the upper recirculation mo sfet after the lower gate voltage falls below the threshold voltage and turns it off before the lower gate voltage rises above the threshold voltage. output overvoltage shutdown the 33899 disables all mosfet outputs when v ignp is above the overvoltage shutdown threshold for a time period greater than t ovs (refer to dynamic electrical characteristics table, page 9 ). output avalanche protection an inductive fly-back event, namely when the outputs are suddenly disabled and v ignp is lost, could result in electrical overstress of the drivers. to prevent this the v ignp input to the 33899 should not exceed 40 v during a fly-back condition. a zener clamp and/o r an appropriately valued capacitor are common methods of limiting the transient. power-on reset (por) on power-up, the vcc and vccl supplies to the 33899 typically increase to 5.0 v and 3.3 v, respectively, within 0.3 ms to 3.0 ms. the 33899 has power-on reset (por) circuitry that monitors both the vcc and vccl voltages. when either voltage falls below its por threshold, the s0 and s1 outputs are driven to the inactive state. when both voltages rise above the por threshold, the outputs are enabled. during por none of the outputs momentarily glitches on. the contents of all spi registers (both di and do) are cleared on each power-on reset cycle. see + 3.3 v input (v ccl ) on page 12 for part requirements to guarantee normal operation. fault detection open load detection is performed in the off state, and short circuit fault detection is performed while the h-bridge circuit(s) are enabled (see figure 13 , page 20 ). however, the user can determine whether an open circuit has caused the output current to go to 0 a via the csns output. all valid faults are latched into the spi fault register and cleared when a logic [1] is written to t he fltclr bit by the system microprocessor (refer to table 8 , page 22 ).
analog integrated circuit device data 20 freescale semiconductor 33899 functional device operation operational modes figure 13. off-state fault detection diagram in the full or half h-bridge mode an open, short to ignition, or short to gnd latches the appr opriate spi fault bits until the fltclr bit is set. any additional faults that occur prior to setting fltclr will be ignored. fault detection during off state fault detection for both the high-side and low-side outputs is done during the off state, when either the en1 or en2 pin is a logic [1], by analyzing th e states of both the high-side and low-side outputs interacting to the external load. s1 is pulled up internally via a high-impedance pullup to v cc , while s0 is pulled down internally to ground. in a normal load state, the low impedance (relative to the internal pull-ups/pull-downs) will force both load connections to about 0.5 v cc . s1 is compared with an internal reference of 0.75 v cc nominally, while s0 is compared to an internal reference of 0.25 v cc nominally. table 7 indicates what status the load will be in based on the combination of the outputs of these two comparators. once any of the above faults are indicated for a period of time exceeding the off-state fault timer, the fault bit will be latched into the spi fault register. the off-state fault timer is started when either the en1 or en2 pin transitions from a logic [1] to a logic [0] (both inputs previously logic [1]) or from a logic [0] to a logic [1] (both inputs previously logic [0]). the off-state filter time is substant ially longer than the on-state to allow energy in the load to dissipate. false open state faults may be set when the outputs are shut down and the load current (reverse polarity only) takes more than the off- state filter time to decay to zero. the microprocessor should clear the open state fault spi bi t and read the fault register again under this condition. 0.75 v cc en2 0.25 v cc s0 s1 v cc of sgfon sbfon fault timer sg f sbf en1 12 k ? 12 k ? note sgfon and sbfon are on-state fault. table 7. off-stat e fault detection s1 s0 load status < 0.75 v cc > 0.25 v cc normal load < 0.75 v cc < 0.25 v cc short to ground > 0.75 v cc < 0.25 v cc open load > 0.75 v cc > 0.25 v cc short to vignp load current (reverse polarity) s0/s1 are at 2.5 vdc, no spi bits set wake up, open fault timer starts open fault timer starts current in load < 0, erroneous open fault spi bit set goo back to sleep t fdo t fdo s0 s1 en1 en2
analog integrated circuit device data freescale semiconductor 21 33899 functional device operation operational modes fault detection during on state while the h-bridge circuit is in operation (i.e., when a high- side mosfet is on), the 33899 is capable of detecting both shorts to vignp and shorts to ground. a short will cause the appropriate mosfets to current limit. the current limit is active for numerous retry peri ods until an overtemperature condition is reached, at which time all outputs are turned off. all on-state faults must be present for a period of time that exceeds the fault time before the 33899 will consider them valid. once they are valid, they are latched until the spi has reported these faults to the microcontroller via the do pin and a logic [1] is written to the fltclr bit. in order for the user to be ce rtain that all detectable on- state faults have been reported, a minimum on time is required for the low-side mosfet. for example, if the pwm frequency is 11 khz, on-state fault detection would not be guaranteed for duty cycles of less than 11%. thermal shutdown the h-bridge has thermal protection circuitry. a thermal fault sets the thermal shutdown bi ts (and any other faults that may be present at that time) and latches off. the h-bridge will remain disabled until the microprocessor sets the fltclr bit (refer to table 8 , page 22 ).
analog integrated circuit device data 22 freescale semiconductor 33899 functional device operation logic commands and registers logic commands and registers spi interface and re gister description spi control register definition an 8-bit spi allows the system microprocessor to clear the fault register, select a programmable current limit, and select a 1x, 2x, or 4x slew rate. the spi control register bit definitions are shown in table 8 . note at por, all bits in the register are cleared to 0s. spi fault register definition the fault diagnostic capability consists of one internal 8-bit fault register. table 9 shows the content of the fault register. the output load status of the h-bridge circuit is reported via the output do spi bits. in addition to output fault information, die temperature warnings and overtemperature conditions are reported. an spi read cycle is limited by a cs logic [1] to logic [0] transition, followed by 8 sclk cycl es to shift the fault register bits out the do pin. the rising edge of cs sets do in a high impedance mode and clears the fault latches if the fltclr bit is set. the thermal fault is immediately set again if the fault condition is still present. accura te fault reporting can only be obtained by reading the do line at intervals greater than the fault timer. a thermal fault will be latched as soon as it occurs. note at por, all bits in the register are cleared to 0s. table 8. spi control register bit definitions 8 (msb) 7 6 5 4 3 2 1 (lsb) fltclr not used not used not used current limit current limit slew time slew time bit 8: fltclr: 0 = retain faults; 1 = clear faults bit 7: not used bit 6: not used bit 5: not used bits 4 ? 3: set low side current comparator limits 00 = 4.0 a 01 = 5.0 a 10 = 6.0 a 11 = 8.5 a bits 2 ? 1: slew time 00 = 1x 01 = 2x 10 = 4x 11 = 4x table 9. spi fault register bit definitions 8 (msb)7654321 (lsb) shvignp shgnd open fault overvoltage or undervoltage ls comparator en1, en2 status die temp die temp bit 8: short to vignp : 0 = no fault; 1 = s1 or s0 shorted to vignp (low-side linear current limit has tripped) bit 7: short to ground: 0 = no fault; 1 = s1 or s0 shor ted to gnd (high-side linear current limit has tripped) bit 6: open fault: 0 = no fault; 1 = s1 or s0 is open circuited bit 5: overvoltage or undervoltage: 0 = no fault; 1 = overvoltage/undervoltage fault bit 4: low-side comparator: 0 = no trip; 1 = tripped bit 3: xor function of en1, en2 inputs. 0 = (en1 same logi c level as en2). 1 = (en1 not same logic level as en2). bits 2 ? 1: die temperature 00 = t < 140 c 01 = 140 c < t < overtemperature shutdown 10 = not defined 11 = overtemperature shutdown (latched off)
analog integrated circuit device data freescale semiconductor 23 33899 packaging package dimensions packaging package dimensions for the most current package revision, visit www.freescale.com and perform a keyword search using the ?98a? listed below. vw suffix 30-pin hsop 98ash70693a issue a
analog integrated circuit device data 24 freescale semiconductor 33899 packaging package dimensions (continued) package dimensions (continued) for the most current package revision, visit www.freescale.com and perform a keyword search using the ?98a? listed below. vw suffix 30-pin hsop 98ash70693a issue a
analog integrated circuit device data freescale semiconductor 25 33899 revision history revision history revision date description of changes 2.0 6/2006 ? initial release
mc33899 rev. 2.0 6/2007 information in this document is provided solely to enable system and software implementers to use freescale semiconduc tor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability ar ising out of the application or use of any product or circuit, and specifically discl aims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data s heets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale se miconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the fa ilure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemni fy and hold freescale semiconductor and its officers, employees, subsidiaries, affili ates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc., 2007. all rights reserved. how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support usa/europe or locations not listed: freescale semiconductor, inc. technical information center, el516 2100 east elliot road tempe, arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate tai po, n.t., hong kong +800 2666 8080 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconductor@hibbertgroup.com

▲Up To Search▲

Price & Availability of 33899

	To Download 33899 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .